In the integrated circuit industry there is a continuing effort to increase microprocessor speed as well as decrease microprocessor device sizes. As microprocessors become more complex, modern microprocessors contain more devices and are pushed to run as fast as possible. These efforts have a number of implications. As integrated circuit device dimensions decrease, the amount of voltage that can be tolerated by such devices also decreases. In addition, as clock speeds increase, integrated circuits become increasingly sensitive to power supply noise and clock skew becomes more critical.
In general, microprocessor integrated circuit operations are typically controlled with a clock. To distribute the clock signal through the large microprocessor integrated circuits of today, a clock distribution network is generally used. Typically, it is necessary for microprocessor designers to use a phase locked loop or some other clock generation element to minimize the delay and skew of a clock signal distributed around a large integrated circuit with the clock distribution network. In addition, it is appreciated that integrated circuit storage elements have minimum hold time requirements. As a result, the minimum delays permitted between storage elements in order to meet hold times can complicate efforts to reduce delay along certain paths. Since the required minimum delay required by integrated circuit storage elements is directly related to the clock skew across a chip, it is noted that these skews must be tightly controlled. In order for a phase lock loop circuit to control effectively clock skew in a distribution network, it is vital that power supply noise is minimized in the integrated circuit.
FIG. 1 shows a prior art power supply noise filter configuration having a portion of an integrated circuit 117, e.g. a microprocessor core, on a chip 101 including a clock distribution network 109B and a phase locked loop 109A. Power is supplied to the chip elements 117, 109B and 109A at V.sub.CC 111. As shown in FIG. 1, the power supply for phase locked loop 109A is filtered through an RC delay circuit comprised of resistor 119 and capacitor 121. Since all of the DC current drawn by phase locked loop 109A flows through resistor 119, the maximum value of resistor 119 is constrained to a relatively small value in order to minimize any DC voltage drop which might occur as a result of DC current flowing through resistor 119.
For example, in the prior art power supply noise filter of FIG. 1, resistor 119 is limited to a maximum value of only ten ohms. In that prior art embodiment, V.sub.CC 111 is equal to 1.8 volts and phase locked loop 109A draws twenty milliamps which causes a 200 millivolt DC voltage drop across resistor 119. Accordingly, only about 1.6 volts is supplied to phase locked loop 109A in the prior art embodiment even though 1.8 volts is supplied at V.sub.CC 111. Since phase locked loop 109A receives less voltage than the portion of integrated circuit 117 and clock distribution network 109B, i.e. 1.6 volts instead of 1.8 volts, the effectiveness of phase locked loop 109A is thereby compromised.
Furthermore, since resistor 119 of the power supply noise filter of FIG. 1 is constrained to a such small value, it is appreciated that a large capacitor is necessary in order to realize a relatively large RC time constant. Thus, if the RC delay of the filter is to be any larger than ten or twenty nanoseconds, an external off chip capacitor is needed since large on chip capacitors are difficult to build. For example, in the prior art configuration shown in FIG. 1, off chip capacitor 121 would need to have a value of 100 microfarads in combination with resistor 119 having a resistance of ten ohms to obtain an RC time constant of one millisecond. It is noted that even though a large external off chip capacitor permits larger RC time constants, the large external capacitor could introduce detrimental effects such as series inductance which would reduce its effectiveness.
As further shown in FIG. 1, the power supplied to clock distribution network 109B is not filtered with the prior art power supply noise filter. The reason why the power supplied to clock distribution network 109B is not filtered is because an excessive DC current would be drawn by clock distribution network 109B thereby resulting in an unacceptable DC voltage drop across resistor 119, assuming that a significant resistance were to be utilized in the incorporation of a useful RC filter. As a result, the portion of integrated circuit 117 of FIG. 1 must suffer the effects of unfiltered power supplied to clock distribution network 109B from V.sub.CC 111 without the benefit of the prior art power supply noise filter.
Therefore, what is needed is a filter to reduce noise from the power supplied to elements of an integrated circuit such a microprocessor. The power supply noise filter would not be limited by the risk of unacceptably high DC voltage drops. In addition, filter elements of the power supply noise filter would be on chip and provide the ability to employ reasonably large RC time constants without the need to use large off chip capacitors. Accordingly, the power supply noise filter could be used to filter noise from the power supplied to a variety of integrated circuit elements. For example, the power supply noise filter may be used to filter simultaneously noise supplied to the phase locked loop circuitry as well as the clock distribution network circuitry of a microprocessor. The power supply noise filter would effectively eliminate the power supply noise induced skew associated with distributing a clock signal throughout a modern large integrated circuit such as a microprocessor.